引用本文:潘春荣,熊文清.稳态调度下单臂组合设备时间延迟分析与优化[J].控制理论与应用,2019,36(10):1719~1729.[点击复制]
PAN Chun-rong,XIONG Wen-qing.Analysis and optimizing of time delay for single-armed cluster tools under steady schedule[J].Control Theory and Technology,2019,36(10):1719~1729.[点击复制]
稳态调度下单臂组合设备时间延迟分析与优化
Analysis and optimizing of time delay for single-armed cluster tools under steady schedule
摘要点击 1969  全文点击 763  投稿时间：2018-07-16  修订日期：2018-12-17
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DOI编号  10.7641/CTA.2019.80527
  2019,36(10):1719-1729
中文关键词  晶圆制造  组合设备  启发式算法  调度  Petri网
英文关键词  wafer fabrication  cluster tools  heuristic algorithm  scheduling  Petri net
基金项目  国家自然科学基金(51665018)，福建省电机控制与系统优化调度工程技术研究中心开放课题(FERC006)
作者单位邮编
潘春荣* 江西理工大学 机电工程学院 341000
熊文清 江西理工大学 机电工程学院 
中文摘要
      在半导体晶圆制造过程中，驻留时间延迟过长对晶圆质量具有消极影响。本文研究单臂组合设备稳态调度中如何合理地分配机械手等待时间，抵消驻留时间延迟的问题。首先，采用Petri网模型描述晶圆制造过程，分析了单臂组合设备稳态调度的时间特性，获得了稳态下工序驻留时间延迟计算表达式。其次，通过解构机械手等待时间对驻留时间延迟的影响机理，提出了一种机械手等待时间分配优先级规则。进一步，将虚拟瓶颈工序用于辅助分配机械手等待时间，结合优先级规则，提出了一种单臂组合设备稳态调度启发式算法。最后，通过例子验证了算法的可行性与有效性。与传统拉式策略和尽早加工策略对比，该算法能有效地减少单臂组合设备稳态调度下的驻留时间延迟并能满足晶圆制造的严格要求。
英文摘要
      In semiconductor wafer fabrication processes, excessive residency time delaying has negative effects on the product quality. This paper is devoted to regulating the robot waiting times in single-armed cluster tools under steady state such that the wafer residency time delay can be offset as much as possible. First, a plant model based on Petri net is built for describing the wafer fabrication processes. Based on the introduced model, analytical expressions for calculating the residency time delay are derived as well as temporal properties of the system. Second, in the light of the deconstruction to the time delay mechanisms caused by the robot waiting, a priority rule for assigning robot waiting times is presented. Third, with the presented priority rule and virtual bottleneck approach, a heuristic algorithm is developed to properly assign the robot waiting time for single-armed cluster tools under the steady state. Finally, illustrative examples are given to validate the feasibility and efficacy of the proposed methodology. Compared with the conventional backward strategy and the earliest starting strategy, the wafer residency time delay can be significantly reduced by the proposed method such that strict wafer residency time constraints can be better met.